100nF

MOSFET gate drivers: from an MCU pin to a half-bridge

Why a microcontroller pin is a poor gate driver, and how an N-channel high side is driven: bootstrap, charge pump, half-bridge IC or transformer.

By switching regulatorshardware

A MOSFET gate is a capacitor, and switching it fast means moving its charge fast: a 50 nC gate in 50 ns is an ampere. The circuit that supplies that ampere, at the right voltage, referenced to the right node, is the gate driver, and the choice of one is mostly the choice of what the source pin is connected to. A low-side switch, source on ground, can be driven from anything with enough current. A high-side switch, source on the load, needs a supply that rides on the switch node — and that is where the bootstrap, the charge pump, the level-shifting driver IC and the isolated drivers come from. This article walks the ladder as Nexperia’s AN90059 and Infineon’s gate-drive note do, with TI’s SLUA887 for the bootstrap arithmetic that the bootstrap capacitor calculator performs. The resistor between the driver and the gate has its own calculator and article.

Low side: the MCU pin, and why it is not enough

The simplest driver is the pin. AN90059: “most MCU GPIO pins can supply 3.3 V or 5 V as a high output … in some cases, the MOSFET can be driven directly from the MCU.” The three limits are the pin’s. Current: “most micro-controllers can only source or sink a small amount of current (usually no more than 10’s of mA)”, so “it takes a long time to switch the MOSFET. Thus, it is only a viable option in low frequency applications and for driving small MOSFETs with low QG.” Voltage: 3.3 V “is suitable for MOSFETs with a typical threshold of around 0.7 V – 1 V”, and the datasheet’s RDS(on) against VGS says what a half-enhanced FET costs. And safety: “in the case of a fault (for example, MOSFET failure), a surge current could flow and the MCU can get damaged”, so the gate resistor is also the pin’s protection.

Three schematics of a low-side N-channel MOSFET switching a load to a supply. Left: an MCU pin drives the gate through a single resistor. Middle: the MCU pin drives the joined bases of an NPN and PNP transistor whose emitters are joined and go to the gate through the resistor; the NPN collector is on the driver supply, the PNP collector on ground. Right: the same totem pole, but its bases are pulled up to a 15 volt supply through a resistor and pulled down by a small NPN that the MCU drives, so the gate swings to about 14 volts.
Fig 1 — AN90059's low-side ladder. An MCU pin "can only source or sink a small amount of current (usually no more than 10's of mA)", so it switches a small, low-threshold FET slowly. The BJT totem pole "takes advantage of the high current gain properties of the BJT to source and sink large peak currents", cannot shoot through, and gives V_GS = V_drive − 0.7 V — weak from a 3.3 V pin. Adding a level shift feeds the bases from 15 V, "a logic high V_GS of around 14.3 V", at the cost of inverting the signal.

The next rung is the BJT totem pole, “an NPN and PNP transistor in a coupled emitter configuration with their bases tied together”, which “takes advantage of the high current gain properties of the BJT to source and sink large peak currents to or from the gate of the MOSFET, enabling the possibility of high-speed switching (for example, up to 100s of kHz)”. It has one property the discrete MOSFET totem pole lacks: “there is no risk of shooting through current since it is not possible for both NPN and PNP transistors to be on at the same time”, because between the bases and the emitters “−0.7 V < VAB < 0.7 V, both BJTs off”. Its price is the same 0.7 V: VGS is Vdrive − VBE, “a weak VGS (for example, VGS = 5 V − 0.7 V = 4.3 V or VGS = 3.3 V − 0.7 V = 2.6 V)”, and on the low side the gate is held at “around 0.7 V”, which “might be an issue if the MOSFET has a low minimum threshold or at high temperature”. A level-shift stage — the bases fed from 15 V through a resistor, a small NPN pulling them down from the MCU — gives “a logic high VGS of around 14.3 V” and inverts the signal.

The complementary MOSFET totem pole gives “full rail-to-rail gate drive voltage” but “they come with the risk of shoot through” during every transition; AN90059’s verdict is that it “is rarely implemented using discrete components”. It is, however, exactly what a gate driver IC is: a rail-to-rail output stage with the dead time built in, which is why the discrete versions are for when there is no IC.

High side, P-channel: easy but slow

A P-channel on the high side has its source on the supply, so pulling the gate to ground turns it on and the drive is ground-referenced — the reason P-channels exist there at all, since otherwise “n-channel MOSFETs are cheaper than equivalent RDSon p-channel devices”, “have lower gate charge for a given RDSon”, and are “usually a preferred choice”. The catch is the turn-off. In AN90059’s circuit an NPN pulls the gate down through RG quickly, but “the turn-off gate current is limited by R1, which is usually quite large, meaning the turn-off is slow for this circuit and it is not suitable for high-speed switching”; making R1 smaller “dramatically increases the power consumption of the driver circuit” because it conducts the whole time the FET is on. Two conditions go with it: “Vsupply must be less than the maximum VGS rating of the MOSFET”, or a Zener clamps the gate, and the kΩ resistors that result mean “the circuit is only suitable for near DC operation”. A P-channel high side is a switch, not a PWM device.

High side, N-channel: the supply has to float

An N-channel on the high side has its source on the switch node. “If the MOSFET is on then Vdd is observed at the source of the MOSFET. Therefore, to keep the MOSFET on, Vdrive needs to be larger than Vdd.” Every high-side N-channel driver is a way of making a gate supply that sits 10–15 V above a node that swings between ground and the bus.

Bootstrap. “A simple and cost-effective way”, two parts: “when the high side FET is off, current from Vsupply flows through the diode and capacitor, charging the capacitor to Vsupply (minus diode VF)”; when the FET turns on and its source rises, “the bootstrap diode becomes reverse biased. The bootstrap capacitor acts as a floating voltage supply for the high side driver circuit for the duration that the MOSFET is on.” The capacitor must be recharged, so “there is a minimum allowed switching frequency and a maximum allowed duty cycle”, and it is “usually implemented in switching applications that have a low side FET, for example, half-bridge, H-bridge, inverter, etc., which pulls the bottom pin of the capacitor to ground for recharging”.

Plot of the bootstrap capacitor voltage over two switching cycles. It starts at 11.3 volts, falls in a straight line during the 90 percent on-time to about 10.8 volts, and recovers in a short exponential during the 10 percent off-time; a dashed line at 8 volts marks the driver under-voltage lockout, well below the droop.
Fig 2 — SLUA887's charge budget in time, for the bootstrap calculator's default case: a 12 V driver with a 0.7 V diode, a 50 nC gate, 10 µA of HB leakage and 100 µA of HB quiescent current at 100 kHz and 90 % duty. Each on-time takes 51.1 nC — 50 for the gate, 1.1 for the driver — and a 100 nF capacitor droops 511 mV, against 3.3 V of headroom to the 8 V UVLO. The 10× rule asks for 44 nF here; the detailed equation only 15.5 nF. At 1 kHz and 98 % duty the driver's current would take a microcoulomb per cycle and the detailed equation would win.

SLUA887 sizes it. The rule of thumb is ten times the gate’s capacitance Qg / (VDD − VF), “to allow for capacitance shift from DC bias and temperature, and also skipped cycles that occur during load transients”; the detailed equation adds the driver’s HB leakage over the longest on-time and its quiescent current over a period, and divides by the headroom to the UVLO threshold, because “values below the minimum required bootstrap capacitor value could lead to activation of the driver’s UVLO therefore prematurely turning off the high-side FET”. Around the capacitor: a VDD bypass ten times larger, a diode that is “a fast recovery diode or Schottky diode with low forward voltage drop and low junction capacitance” rated above the bus, and a small resistor to limit the start-up peak — the note’s scope shots show 0 Ω disturbing both driver outputs where 2.2 Ω did not.

Charge pump. For the cases bootstrap cannot do — “if the duty cycle is too high, or switching frequency is too low, or if the low side component does not allow for sufficient charging of the bootstrap capacitor” — two diodes and two capacitors driven by a square wave make “a voltage of 2·Vsupply” on a tank capacitor. “Contrary to the bootstrap, the advantage of charge pump is that it has no minimum frequency or maximum duty cycle limitations. However, it requires more components and complexity”: AN90059’s full version adds a Zener regulator to hold VGS near 11 V, an undervoltage lockout “so that the MOSFET does not switch unless there is a suitable amount of gate drive supply voltage”, and a push-pull stage. It is how a high-side N-channel is held on at DC.

Half-bridge driver ICs. The integrated version of the bootstrap, with the level shifting inside. Infineon: “the high-side gate drive output is not referenced to 0 V and instead switches between VS and VB”, the high-side section “is floating with respect to 0 V”, and it is set and reset “by pulses transferred from the low-side through high-voltage level-shift MOSFETs within the IC”. The IC adds the dead time “to allow time for the first MOSFET to switch off fully before the second one switches on”, keeps the bootstrap’s duty limit (“a minimum pulse width at LO is necessary to allow replenishment of the bootstrap capacitor”), and adds ratings of its own: “dv/dt and negative VS ratings”, the latter because on a real bridge the switch node “swings below the level of the negative DC bus due to the parasitic inductances”. Available “from 100 to 1200 V”, which “is the voltage rating of the internal level-shift MOSFETs and the high-side circuitry on the IC die”.

Isolated drives: when the control side must not touch the power

Above a few hundred volts, or where an operator can touch the low side, “it is desired to have the control circuitry isolated from the power switch side”. Both isolated families “have the flexibility to drive either high side or low side MOSFETs since the secondary side can be floating”.

Pulse transformer. The drive goes through a DC-blocking capacitor “needed on the primary side to ensure that the average voltage on the primary coil is zero”, because otherwise “the current through it would continue to drift until the coil reached saturation”. The transformer has “a maximum volt-time rating”: AN90059’s example, “100 kHz, the duty cycle is 50 %, and the voltage on primary coil is switching between −6 V and +6 V, then the volt-second product is 6 V·5 µs = 30 Vµs”. The blocking capacitor is also the limit.

Two square-wave plots of the voltage on a pulse transformer primary after the DC-blocking capacitor. At 50 percent duty the wave swings symmetrically between plus 6 and minus 6 volts. At 20 percent duty the positive pulse is short and tall, plus 9.6 volts, and the negative part long and shallow, minus 2.4 volts; the shaded areas above and below zero are equal in both.
Fig 3 — Infineon's figure 26 computed: a 0–12 V drive through the DC-blocking capacitor "required to balance the transformer flux (volt-seconds)". The capacitor removes the average, so the positive level is V(1 − D) and the negative −V·D and the two areas match. At 50 % that is ±6 V; at 20 % the on-pulse is +9.6 V and the off-level −2.4 V. "As duty cycle increases, the positive voltage falls and the negative voltage rises" — which is why "they cannot be used with high duty-cycle pulses": at 90 % the gate would see +1.2 V on and −10.8 V off.

Infineon: “as duty cycle increases, the positive voltage falls and the negative voltage rises to keep the volt-second product equal”, so pulse transformers “cannot be used with high duty-cycle pulses”, and there is “a minimum frequency requirement, which is dependent on the size and volt-time rating of the transformer”. A DC restorer on the secondary (a capacitor and diode) puts the offset back where the FET needs a 0-to-V gate; driving the primary from two PWM outputs removes the blocking capacitor and its start-up resonance.

Optocoupler. Good isolation and no duty limit — “their capability to drive both DC and switching applications” — but “optocouplers are often slower devices, with propagation delays that can reach several microseconds”, their insulation “can degrade” over time, “they also require a secondary-side voltage supply, which can be floating or boosted if driving a high-side FET”, and “a high dV/dt on the output side can induce current spikes due to the optocoupler’s intrinsic capacitance, which may cause unwanted switching”.

Isolated driver ICs. Infineon’s coreless-transformer parts move the transformer onto the die — “an on-chip transformer consisting of metal spirals and silicon oxide insulation” — for “short propagation delays, excellent delay matching”, and reinforced isolation to the kilovolt standards it lists. They still need what any isolated driver needs: “floating power supplies connected from VDDx to GNDx referenced to the sources of each MOSFET”, which for a multilevel converter means “a low-power flyback or fly-buck power supply with multiple isolated outputs”.

Two things every driver needs

Faster off than on. “In most applications, optimizing turn-off speed is more critical than turn-on speed, particularly in half-bridge or DC-DC converters”, because a fast turn-on raises the other switch’s diode-recovery current, and “turn-off is typically slower than turn-on when using a single gate resistance”. The standard fix is a diode across the gate resistor with a smaller RG_OFF — “in some cases, RG_OFF can be set to 0 Ω” — or a PNP at the gate that pulls it down locally and “reduces loop inductance by positioning the PNP transistor near the MOSFET”, at the cost of about 0.7 V on both levels.

A known state with no drive. A gate-source resistor in the kΩ range, Infineon’s “typically 10 kΩ”, “so that the MOSFET gate will be discharged if the gate becomes disconnected from the driver circuit”, and AN90059’s “known state (off) in the case of a fault with the gate drive circuit or when there is no power”. A Zener clamp where the supply can exceed the gate rating, minding its capacitance. And attention to gate bounce at turn-off, which “can cause large, undesirable shoot-through current in a half bridge” and is reduced “by adding an external CGS or by reducing the gate drive impedance” — the driver’s low impedance is the protection, and the kΩ pull-down is not a substitute for it.

Choosing

  • Low side, slow, small FET: the pin and a resistor, with a logic-level part.
  • Low side, fast: a driver IC; or the BJT totem pole with a level shift where there is none.
  • High side, on or off for long periods, low frequency: a P-channel with a level shifter, or an N-channel with a charge pump.
  • High side in a bridge, switching continuously: a half-bridge driver IC with a bootstrap sized by SLUA887’s budget, a fast diode, a small series resistor and a bypass ten times the bootstrap.
  • Above a few hundred volts, or safety isolation: an isolated driver IC with a floating supply per switch; a pulse transformer where the duty cycle stays moderate; an optocoupler where microseconds are acceptable.

Sources