How ESD protection works: why layout is half of the diode

Electrostatic discharge is a person, a cable or a tool arriving at a connector carrying a few thousand volts on a few hundred picofarads, and letting go of it in a nanosecond. NXP’s ESD design guide puts the human side of it plainly: “the human body has the ability to charge and store energy with a charge that can reach several thousands of volts (8 kV to 10 kV is common) and peak currents from 1 A up to 200 A”, delivered with a rise time of “200 ps to 20 ns”. The test that products are qualified against, IEC 61000-4-2, standardises it as 150 pF charged to the test voltage and discharged through 330 Ω, and its level 4 is 8 kV by contact or 15 kV through the air.

ESD protection works by giving that current somewhere to go before it reaches a chip. The part that does it — a TVS, a transient voltage suppressor — is a diode array that does nothing at the line’s normal voltage and breaks down a volt or two above it, shunting the discharge to ground so hard that TI’s example data sheet holds the line at 10.4 V while 16 A flows through it. That is the diode’s half. The other half is the copper between the connector, the diode and ground: TI’s layout guide works out that an 8 kV strike’s current rises at 4 × 10¹⁰ A/s, so “even with 0.25 nH of inductance an additional 10 V is presented to the system”. This article is what the discharge is, what the diode does with it, and why the second half decides whether the first half was worth fitting. The TVS clamping calculator does the diode’s arithmetic; the layout’s is below.

What a discharge is

IEC 61000-4-2 is a circuit. AN10897 draws it: a high-voltage supply charges a 150 pF capacitor through 50–100 MΩ, and a switch dumps it into the equipment through 330 Ω. The first peak of current is therefore about the test voltage over 330 Ω, and the note’s table gives it for each level alongside the human body model that chips are qualified against — 100 pF through 1.5 kΩ:

Test voltage	HBM peak (100 pF / 1.5 kΩ)	IEC peak (150 pF / 330 Ω)	IEC class
2 kV	1.33 A	7.5 A	1
4 kV	2.67 A	15.0 A	2
6 kV	4.00 A	22.5 A	3
8 kV	5.33 A	30.0 A	4 (contact)
10 kV	6.67 A	37.5 A	—

The two columns are the reason a chip that “passes 2 kV HBM” is not a protected product. AN10897: “there is a fundamental difference between system-level and device-level testing” — the device test qualifies a bare part for handling on a production line, the system test is a finger on a connector, and at the same voltage the system test delivers five and a half times the current and far more energy. “The IEC specification ESD waveform has similar characteristics, however, the amount of energy delivered is far greater than a HBM pulse.”

The energy is ½CV². For 150 pF at 8 kV that is 4.8 mJ, and at the 15 kV air-discharge level 17 mJ. (AN10897’s text says “150 pF × 8 kV is approximately 1 µJ”, which is not what its own equation gives; the figure and the numbers here use the arithmetic.) Delivered in the tens of nanoseconds the pulse lasts, 4.8 mJ is a peak power in the hundreds of kilowatts — into a pin whose ESD structure is designed for the HBM’s fraction of it.

The rise is the part that matters most. TI’s layout guide draws the level 4 waveform with an “800 ps 90/10 rise time” to its 30 A peak; NXP gives 0.7 to 1 ns. Everything about protecting against ESD follows from current changing that fast.

What the diode does

A TVS is, in SLVA680’s words, “an array of diodes arranged to present a very high impedance to the voltages normally present in the circuit, but if voltages exceed the design, the TVS diodes will breakdown and shunt I_ESD to ground before it can damage the system being protected.” SLLA305 walks a data sheet’s numbers for one, and they are the whole mechanism in five lines:

• Working voltage V_RWM, ±5.5 V in its example: “the recommended operating voltage of the protected line”, below which the diode leaks 50 nA and does nothing else.
• Breakdown V_BR, 8 V: “the limit where the ESD device starts to conduct significant amounts of current when exceeded”.
• Dynamic resistance R_DYN, 0.19 Ω: “the steepness of the device’s I-V curve” above breakdown.
• Clamping voltage V_CLAMP, measured with a transmission-line pulse: 7.6 V at 1 A, 8.2 V at 5 A, 10.4 V at 16 A. SLLA305 maps the TLP current to the IEC strike — 4 A for 2 kV, and “for most ESD devices, the clamping voltage is specified at 16-A/8-kV IEC”.
• Line capacitance C_L, 0.5 pF: what the diode costs the signal, and why a USB or HDMI line needs the low-capacitance part.

Read the curve from the right: 30 A of IEC strike, taken as 16 A of TLP, lifts the pin to 10.4 V. A logic input with a 3.6 V absolute maximum does not survive 10.4 V by much margin, and that is the good case — the diode alone, with nothing in series. SLLA305’s clamping voltages are measured with the pulse applied at the diode’s pins.

Why the layout is the other half

The current does not arrive at the diode’s pins. It arrives at a connector, travels along copper to the diode, through the diode to its ground pad, and through more copper and vias to wherever the ground plane is. SLVA680 writes the voltage at the protected chip as

$V_{ESD} = V_{BR} + R_{DYN}\,I_{ESD} + L\,\frac{dI_{ESD}}{dt}$

and evaluates the last term: “in an 8 kV ESD event as specified by IEC 61000-4-2, the dI_ESD/dt = (30 A)/(0.8 × 10⁻⁹ s) = 4 × 10¹⁰ A/s. So even with 0.25 nH of inductance an additional 10 V is presented to the system.” A nanohenry is 40 V. A via is of the order of a nanohenry. A centimetre of trace is several.

That is the arithmetic behind every ESD layout rule, and SLVA680’s four are these. Between the connector and the TVS: nothing — “minimize any inductance between the ESD source and the path to ground through the TVS”, with “generally, placing a via between the ESD source and the TVS is detrimental”. Between the TVS and ground: “minimizing inductance between the TVS and ground is critical” — “the TVS ground pin should connect to a same layer ground plane that is coupled with another ground plane on an immediately adjacent layer … with one via immediately adjacent to the ground pin of the TVS”. Around the strike path: it is an antenna while the current rises, so “unprotected circuits should not be adjacent to an ESD protected circuit’s traces between the ESD source and the TVS”, and the corners on that trace “should not exceed 45° or, ideally, … curved with large radii”. And the ground itself: “a chassis ground for the TVS that is separated from the digital and/or analog ground by inductance provides very good protection”, with the chassis screw “immediately adjacent to the TVS ground and the ESD source’s ground (for example, a connector shield)”.

The TVS article is the placement in detail. The point here is only the size of the term: a diode with a 10 V clamp on a layout with 2 nH in the loop is a 90 V clamp during the rise. The datasheet number is the left end of the line in the figure; the board decides where on it the pin sits.

Where the current goes after the diode

The diode moves the strike to ground; it does not make it disappear. AN10897 describes what a discharge does inside equipment once it is in: “the high frequency components will flow radially, whereas the low frequency components will seek the path of least resistance to ground. This current flow will excite any existing antennas … for ESD events, even a 1/20 wave length antenna may conduct a significant amount of energy.” A ground plane that carries 30 A for a few nanoseconds has a voltage gradient across it, and every circuit referenced to two points of that plane sees the difference — the “ground shift” SLVA680’s grounding advice is about. That is why the TVS ground goes to chassis where a chassis exists, and why the connector shield, the TVS and the chassis screw sit together.

NXP sorts the outcomes into three: “temporary errors that are automatically corrected”, “temporary errors that require some intervention by the operator”, and “permanent damage that requires repairing or replacing part or all of the EUT”. The diode and the layout prevent the third. The first two are usually the ground shift and the radiated field reaching a reset line, a clock or an ADC reference, and they are found in the EMC lab, not on the schematic.

What “an ESD protection circuit” is

Three elements, in order from the connector inward, and not all of them always present:

1. Something to make the current small. Series resistance limits the current a pin can receive: AN10897’s example is that “to limit 6 kV ESD event current to 10 mA requires 600 kΩ” — possible on a slow input, impossible on a data line, which is why data lines get a diode instead.
2. Something to divert it. The TVS, placed at the connector with its ground pad on the plane, sized by working voltage against the line and clamp voltage against the chip’s absolute maximum — the TVS clamping calculator.
3. Something to slow it. A capacitor to ground on a slow line absorbs charge and lowers the peak; a ferrite in series adds impedance at the discharge’s frequencies. Neither is a substitute for the diode on a fast line, where the capacitance is not affordable.

And the thing that is not on the schematic at all: the inductance of the copper between them, which SLVA680’s equation says is worth 40 V per nanohenry at 8 kV. A protection circuit is the diode and its loop.

Worked numbers

IEC 61000-4-2 level 4     150 pF at 8 kV through 330 Ω
first peak               30 A, rise 0.8 ns                   dI/dt = 4 × 10¹⁰ A/s
energy                   ½ × 150 pF × (8 kV)²                = 4.8 mJ   (15 kV air: 17 mJ)

SLLA305's example diode  V_RWM ±5.5 V, V_BR 8 V, R_DYN 0.19 Ω, C_L 0.5 pF
clamp at the pins        16 A TLP ≙ 8 kV                     = 10.4 V

with layout inductance   V = 8 + 0.19 × 30 + L × 4 × 10¹⁰
   0.25 nH                                                    = 23.7 V   (SLVA680: "+10 V")
   1 nH (one via)                                             = 53.7 V
   2 nH                                                       = 93.7 V

The diode’s job is the 10.4 V. The layout’s job is not to add 80 V to it.