Via

What one plated hole can carry, how much it drops, and how much heat it conducts through the board. The barrel is treated as a conductor with the cross-section of its plating, which is what the IPC current curves are fitted over.

Fig 1 — Barrel section, 25.5 × 10⁻³ mm² of plated copper.

Finished hole (mm)

Plating thickness (µm)

Board thickness (mm)

Temperature rise (°C)

Copper temperature (°C)

Vias in parallel

Target current (0 to skip) (A)

Pad diameter (mm)

Antipad diameter (mm)

Dielectric constant (εr)

Current: 951 mA
Resistance: 1.05 mΩ
Thermal resistance: 162.8 K/W
Copper cross-section: 25.5 × 10⁻³ mm²
Same copper as 1 oz trace: 0.74 mm wide
Inductance: 1.25 nH
Capacitance to planes: 0.573 pF

Reference

Standard: IPC-2221A Section 6.2 (internal-layer curve); IPC-6012 (plating thickness)

A  = π · ((d/2 + t)² − (d/2)²)        plated copper cross-section
R  = ρ · L / A · (1 + 0.00393 · (T − 20))    ρ_Cu = 1.68e-8 Ω·m
I  = 0.024 · ΔT^0.44 · A_mils²^0.725      IPC-2221 internal curve
θ  = L / (385 W/m·K · A)                   conduction through the barrel only
L  = 5.08 · h · (ln(4h/d) + 1) nH         h, d in inches (Johnson & Graham)
C  = 1.41 · εr · h · D_pad / (D_antipad − D_pad) pF

Assumptions

Uniform plating over the full barrel length; real barrels thin toward the middle.
Current capacity uses the internal-layer curve because the barrel is buried in laminate. IPC-2152 measured vias and found them slightly better than this.
Thermal resistance is the copper only. In practice the laminate around the via and the pads on each end carry a useful share of the heat.
Vias in parallel share current equally — true only if they are the same size and placed symmetrically.
DC. At high frequency current crowds toward the outer wall.
Inductance and capacitance are the usual lumped approximations; they are fine for deciding whether a via matters at your edge rate, not for modelling one at 10 GHz.

What it computes

A plated through-hole is a thin copper tube. Everything the calculator reports follows from the cross-sectional area of that tube, which is the annulus between the finished hole and the outside of the plating:

r_in  = d / 2                     d = finished hole diameter
r_out = r_in + t                  t = plating thickness
A     = π · (r_out² − r_in²)

Note that d is the finished hole, the number on the drill drawing. The drill itself is larger by 2·t; the fab picks it.

Given A, three things fall out.

R = ρ · L / A · (1 + α · (T − 20))     ρ_Cu = 1.68e-8 Ω·m, α = 0.00393 /°C
I = 0.024 · ΔT^0.44 · A_mil²^0.725      IPC-2221 internal-layer curve
θ = L / (k_Cu · A)                      k_Cu = 385 W/(m·K), copper only

Resistance is plain Ohm's law over the barrel length, corrected for the operating temperature. Current capacity applies the IPC-2221 (Section 6.2) internal-layer curve to the barrel area, exactly as it would to a buried trace of the same cross-section. That is what Saturn PCB, KiCad and Altium do, and IPC-2152 later measured vias and found they run slightly cooler than the equivalent trace, so it errs on the safe side. Thermal resistance is straight conduction through the copper wall, treating the barrel as a slab of length L and area A.

N identical vias in parallel divide resistance and thermal resistance by N and multiply current by N. The "equivalent trace width" line answers a question that comes up every time: how wide a trace of a given copper weight has the same copper as one barrel.

Plating thickness: IPC-6012

IPC-6012 (Qualification and Performance Specification for Rigid Printed Boards) sets the minimum average copper plating in the hole wall. The figures that matter:

Class	Minimum average	Thin-area minimum	Typical use
Class 1	20 µm	18 µm	Consumer, limited life
Class 2	20 µm	18 µm	Most commercial and industrial boards
Class 3	25 µm	20 µm	Aerospace, medical, anything that must not fail

Most quick-turn fabs plate to around 20–25 µm; some advertise 18 µm as the default. If a via is carrying real current, put the plating requirement on the fab drawing rather than assuming it.

Worked example

0.3 mm finished hole, 25 µm plating, 1.6 mm board, 20 °C, 10 °C allowed rise, four vias in parallel.

r_in   = 0.15 mm             r_in²  = 0.0225 mm²
r_out  = 0.15 + 0.025 = 0.175 mm   r_out² = 0.030625 mm²
A      = π · (0.030625 − 0.0225) = π · 0.008125 = 0.02553 mm²
       = 0.02553 · 1550 = 39.56 mil²

Resistance
R = 1.68e-8 · 0.0016 / 2.553e-8 = 1.053e-3 Ω = 1.05 mΩ   (at 20 °C, factor = 1)

Current, IPC-2221 internal
10^0.44        = 2.754
39.56^0.725    = 14.39
I = 0.024 · 2.754 · 14.39 = 0.951 A

Thermal resistance
θ = 0.0016 / (385 · 2.553e-8) = 162.8 K/W

Four in parallel
R = 1.053 / 4 = 0.263 mΩ     I = 4 · 0.951 = 3.80 A     θ = 162.8 / 4 = 40.7 K/W

Equivalent 1 oz trace
W = 0.02553 / (1 · 0.0347) = 0.736 mm

One 0.3 mm via is worth a 0.74 mm 1 oz trace, and is good for about 1 A at a 10 °C rise by the conservative curve. Real-world it will take two or three amps before it gets warm, which is why "1 A per via" is a workable rule of thumb with margin built in.

Thermal vias under a QFN pad

The thermal figure is the one people actually use. A typical exposed-pad QFN has a 4 × 4 mm pad with 0.3 mm vias on a 1.0–1.2 mm pitch, nine to sixteen of them. With the numbers above, nine vias give 162.8 / 9 = 18 K/W and sixteen give 10 K/W, barrel conduction only. Stack that against the package's own θ_JC(bottom) of 1–5 K/W and the spreading on the far-side copper of 20–60 K/W per square inch and it is clear the array is not the bottleneck past a dozen or so vias; the copper area on the other side is. TI's SNVA419 and SLOA120 both come to the same place: fill the pad with vias at ~1 mm pitch, then spend effort on the plane area, not on more vias.

Filling the barrels with solder or conductive epoxy lowers θ per via by roughly a third (solder conducts at ~50 W/(m·K), not 385, but it fills the whole 0.3 mm bore); the bigger reason to fill is the assembly issue below.

Where it stops being valid

Plating is not uniform. Plating current density is lowest mid-barrel, so the wall thins toward the centre of a thick board; the ratio between board thickness and hole diameter (aspect ratio) sets how bad it gets. Past about 8:1 assume the thin-area minimum, not the average. Resistance and current both scale with the thinnest point.
Microvias are a different animal. Laser-drilled blind vias (0.1 mm, one layer deep) are often fully filled with plated copper. Treat those as a solid cylinder, not a tube, and the area is π·r² — the tool will underestimate them.
The IPC-2221 curve was not fitted to vias. It is a trace curve applied to an equal area. IPC-2152 reports that vias in the same net as the trace they connect barely change the trace's temperature, so this is conservative. A via carrying current into a plane is a better heat sink than the curve assumes.
Thermal figure ignores the laminate and the pads. FR-4 at 0.3 W/(m·K) is a poor conductor but there is a lot of it; the pads at each end spread heat into the copper layers. The barrel-only figure is an upper bound on θ per via, and the whole-array θ is dominated by what is on the other side.
DC only. At RF the current lives on the outer wall's skin and the via is an inductor (roughly 1 nH per mm of length) more than a resistor. Use the via inductance/stub figure for signal work.

Common mistakes

Via-in-pad without filling. An open via in a QFN or BGA pad wicks solder down the barrel during reflow. The joint ends up starved, or the part floats, or solder shows up on the other side. Either fill and cap the via (IPC-4761 type VII, which costs money) or use a slightly smaller via with a solder mask tent and accept a small void. For the QFN pad specifically, "windowed" solder paste apertures covering ~60–80 % of the pad help, but they do not stop wicking into open holes.
Vias on both sides of the paste layer. The vias are meant to move heat, so they need copper on the far side. A pad array with the bottom layer solder-masked and no copper pour underneath conducts to nothing.
Sharing current unequally. Four vias in a line along a trace do not carry a quarter each; the first sees most of it. Put the vias in a row across the current direction, or in a block, and keep them the same size.
Thermal reliefs on power vias. A relief spoke of 0.25 mm on a via that is supposed to carry 2 A is a fuse. Use direct connections on power and thermal vias, and accept the harder rework.
Reading the drill size as the finished hole. A 0.3 mm drill is a roughly 0.25 mm finished hole; the plating comes off the drill diameter, not on top of the finished one. The calculator wants the finished hole.
Counting on class 3 plating from a class 2 fab. The default is 20 µm average and may be 18. Write it on the drawing if the current calc depends on 25.

Via