Decoupling

What it computes

A capacitor is a series RLC. Below its self-resonant frequency the capacitance sets the impedance; above it, the inductance does, and the value printed on the part stops mattering. ESR is the floor at resonance.

|Z|   = √( ESR² + (2πfL − 1/(2πfC))² )
f_srf = 1 / (2π √(L C))
L     = body ESL (package preset) + mounting inductance

Body ESL presets: 0201 0.3 nH, 0402 0.4 nH, 0603 0.6 nH, 0805 0.8 nH, 1206 1.2 nH, reverse-geometry 0306 0.2 nH. The mounting field is where the real number lives. The second half is the target-impedance method from XAPP623:

Z_target = V_dd · ripple / ΔI      the rail must stay under this
f_max    = 0.35 / t_rise           up to roughly this frequency

For a band, it finds the worst impedance of one part and divides: N identical capacitors in parallel have 1/N the impedance, so N = ceil(Z_worst / Z_target). Identical parts only; mixed values are the anti-resonance section.

Worked example

The part this site is named for: 100 nF, 0402, ESR 20 mΩ, 0.4 nH body, 0.6 nH mounting, 1 nH total.

f_srf = 1 / (2π √(1e-9 × 1e-7)) = 1 / (2π × 1e-8) = 15.9 MHz

at 100 kHz:  1/(2πfC) = 1/(2π × 1e5 × 1e-7) = 15.92 Ω
             2πfL     = 2π × 1e5 × 1e-9      = 0.0006 Ω
             |Z| = √(0.02² + (0.0006 − 15.92)²) = 15.9 Ω

at 15.9 MHz: reactances cancel              |Z| = ESR = 20 mΩ

at 1 GHz:    2πfL     = 2π × 1e9 × 1e-9      = 6.283 Ω
             1/(2πfC) = 1/(2π × 1e9 × 1e-7)  = 0.0016 Ω
             |Z| = √(0.02² + 6.28²)          = 6.28 Ω

At 1 GHz the part is a 1 nH inductor; a 1 nF in the same footprint reads the same 6.28 Ω.

Target impedance for a 1 V core rail, 5 % ripple, 10 A step, 1 ns edge:

Z_target = 1 V × 0.05 / 10 A  = 5 mΩ
f_max    = 0.35 / 1e-9        = 350 MHz

How many of the 100 nF above to hold a gentler 100 mΩ from 1 to 100 MHz:

at 1 MHz:    1/(2πfC) = 1.5915 Ω, 2πfL = 0.0063 Ω
             |Z| = √(0.02² + 1.585²)         = 1.59 Ω     ← worst in band
at 100 MHz:  2πfL = 0.628 Ω, 1/(2πfC) = 0.016 Ω
             |Z| = √(0.02² + 0.612²)         = 0.61 Ω
N = ceil(1.59 / 0.1)                         = 16 parts

Sixteen 100 nF parts to cover 1 MHz, where one 4.7 µF (34 mΩ there) would do it alone: bulk at the bottom of the band, small parts at the top. The 5 mΩ target is a plane and package problem, not a count.

Where it stops being valid

Why 100 nF. At 1 nH it resonates at 16 MHz, the middle of the edge spectrum of 1990s logic. A 1 µF in the same footprint has an SRF of 5 MHz and the same 100 MHz impedance. The value is a habit; the inductance is the spec.

Mounting inductance is usually larger than the body.A via or a narrow trace is roughly 1 nH per millimetre. An 0402 with vias at the pad ends and the plane pair 0.2 mm down adds 0.3 to 0.5 nH. A 2 mm trace from pad to via adds 2 nH; vias 1.5 mm down to a mid-board plane add 1.5 to 3 nH more. Two capacitors sharing a via pair share its inductance and do not parallel. The 0.6 nH in the example is a good layout; 2 to 4 nH is a careless one, which puts the 100 nF SRF at 8 or 6 MHz and doubles or quadruples the 100 MHz impedance.

Mixed values anti-resonate. Put a 100 nF and a 10 nF side by side, each with 1 nH. Between their SRFs (16 and 50 MHz) the 100 nF is inductive and the 10 nF capacitive: a parallel LC tank, and the combined impedance peaks with a height set by ESR. At 30 MHz the 100 nF is 0.19 Ω inductive, the 10 nF 0.34 Ω capacitive, and the pair is 0.4 Ω, worse than the 100 nF alone. Decade ratios with low-ESR ceramics are the worst case. XAPP623 and UG483 use many values spaced about 3:1 with enough of each to flatten the peaks; the other school uses many identical parts and accepts a lower SRF for no peaks at all. Both work; one each of three decades does not.

Above 100 MHz the caps are gone. One 100 nF at 1 nH is 0.63 Ω at 100 MHz; forty are 16 mΩ, but the spreading inductance of the plane between them and the BGA is about as much. From roughly 100 MHz up the die is fed by the plane pair (a few hundred pF per square inch at 0.1 mm spacing, almost no inductance) and the package's own capacitance. The 5 mΩ, 350 MHz target above is met with a thin power-ground dielectric and on-package capacitance, not more 0402s.

Below the regulator's bandwidth it holds the rail. A switcher's loop closes at tens of kHz, an LDO's at a few hundred kHz. Between that and where the 100 nF parts arrive, a 10 to 100 µF bulk part carries the load; its ESR matters, and so does the regulator's stability with it.

ESR and ESL are constants here. Real MLCC ESR falls with frequency, and class 2 dielectrics lose capacitance with DC bias, which moves the SRF up. Expect a factor of two; a two-port shunt measurement on a VNA finds the rest.

Common mistakes

• Choosing a capacitor by value for a high-frequency job. Above the SRF the value is irrelevant; choose the package and the mounting.
• Placing the via at the end of a trace instead of at the pad. The trace adds more inductance than the whole body of the part.
• Sprinkling 100 nF, 10 nF and 1 nF next to each pin "for broadband coverage". With one of each, that is two anti-resonance peaks and no broadband anything.
• Expecting board capacitors to fix a die-level ripple problem. If the edge is 1 ns, the on-board network is finished by a few hundred MHz; the rest is package and plane.
• Forgetting the DC bias on a small class 2 part. A 0402 100 nF 10 V X5R at 5 V may be 50 nF, and the SRF moves accordingly.

Further reading

• Xilinx XAPP623, Power Distribution System Design: Using Bypass/Decoupling Capacitors — target impedance, capacitor resonance, how many of each value, plane capacitance; the decades school laid out with numbers.
• ADI MT-101, Decoupling Techniques — the series RLC view, ferrite plus capacitor filters, and placement for analog parts.
• TI SCBA007, The Bypass Capacitor in High-Speed Environments — ESL and ESR by package with measured inductance, and why one 100 nF is not a broadband short.
• TI SPRA230, Guidelines for Using Decoupling Capacitors on DSP Designs — short and practical: bulk versus local, value selection, placement.