RC filter

What it computes

One resistor in series, one capacitor to ground. The capacitor's reactance falls with frequency, so the divider it forms with R passes DC and rolls off above the frequency where X_C equals R. That is the corner, and everything else follows from the time constant τ = RC.

fc = 1 / (2π · R · C)              −3 dB point; |H| = 1/√2, phase −45°
τ  = R · C                         step reaches 63 % at τ, 99 % at 4.6 τ
tr = ln(9) · τ ≈ 2.2 · τ           10 % to 90 % rise time on a step
|H(f)| = 1 / √(1 + (f/fc)²)        −20 dB/decade well above fc

Nothing here comes from a standard; it is the first-order low-pass from any circuits text (Horowitz & Hill, The Art of Electronics, section 1.7). The 2.2 τ figure is the one with consequences: it links the filter to the edge you are filtering, and through BW ≈ 0.35 / t_r it links back to bandwidth. The tool solves for whichever of f_c, R or C you leave out and reports τ and t_r for the pair.

Worked example

An ADC input with a 4.7 kΩ series resistor and 10 nF to ground.

τ  = 4700 × 10e-9      = 47.0 µs
fc = 1 / (2π × 47e-6)  = 1 / 2.953e-4 = 3.39 kHz
tr = 2.2 × 47 µs       = 103 µs

The calculator gives 3.39 kHz, 47.0 µs and 103 µs. Going the other way, solving for the capacitor that puts a 10 kΩ source at 1 kHz:

C = 1 / (2π × 1000 × 10 000) = 15.9 nF   →  fit 15 nF (1.06 kHz) or 18 nF (884 Hz)

Now the two things the formula does not know about. Suppose the signal comes from a 1 kΩ source (a sensor output, an op-amp with a series isolation resistor) and feeds a 100 kΩ load:

Source impedance adds to R:
  R' = 4.7k + 1k = 5.7 kΩ      fc = 1 / (2π × 5700 × 10n) = 2.79 kHz

Load in parallel with C, Thévenin:
  R_th = 4.7k ∥ 100k = 4.49 kΩ  fc = 1 / (2π × 4490 × 10n) = 3.55 kHz
  DC gain = 100 / 104.7 = 0.955  = −0.40 dB

Make the series resistor 100 kΩ to save current and the same load halves the signal.

Where it stops being valid

Cascading two sections. Two identical RCs in a row do not give −6 dB at f_c and −40 dB/decade from there. Twobuffered sections do: each contributes −3 dB, and the pair reaches −40 dB/decade well above the corner. Unbuffered, the second section loads the first and the transfer function is 1 / (1 + 3sτ + s²τ²). At the design f_c that is 20·log(1/3) = −9.5 dB, the real −3 dB point has dropped to about 0.37 f_c, and the two poles are spread apart (at 0.38/τ and 2.62/τ), so the slope only reaches −40 dB/decade a decade above the higher one. The usual fix is to make the second stage ten times higher in impedance (R₂ = 10 R₁, C₂ = C₁/10) so the loading is a few percent; the better fix is a buffer, or a proper second-order Sallen-Key if you need a defined corner.

Anti-aliasing for an ADC. A single pole is 20 dB per decade. Sampling at 10 kHz with f_c at 1 kHz attenuates a 9 kHz interferer (which aliases to 1 kHz) by only about 19 dB. A 12-bit converter wants 72 dB. So a single RC is an anti-alias filter only when the oversampling ratio is large: sigma-delta parts at 1 MHz modulator rates, or SAR parts oversampled in firmware. For a SAR sampling near Nyquist, the RC's job is different. It is a charge reservoir for the sample-and-hold: C should be 10 to 20 times the ADC's sampling capacitor and R small enough that the reservoir recharges within the acquisition time, which for a 10 pF hold cap and 1 µs acquisition means well under 10 kΩ. Those two constraints, not the corner, set the values; check them against the ADC datasheet's R_source maximum.

Fast edges. Above a few MHz the capacitor's ESL and the resistor's parasitic capacitance appear. A 0603 MLCC self-resonates in the tens of MHz and looks inductive above that; a 10 kΩ thick-film resistor has 0.1 to 0.2 pF across it, which at 100 MHz is 8 kΩ of bypass. The roll-off flattens well short of the floor you expected.

Ceramic DC-bias derating. The C in the formula is the capacitance the part actually has at its operating voltage. Class 2 ceramics (X5R, X7R) lose capacitance with DC bias, badly so in small packages: a 0402 10 V X5R at 3.3 V can be at 60 % of nominal, a 0603 16 V X7R at 5 V is often at 70 to 80 %. Würth ANP062 has the curves. The corner moves up by the same factor. For a filter on a biased node, use C0G/NP0 (no bias effect, but only up to a few tens of nF), a physically larger package with a higher voltage rating, or size the corner with the derated value from the manufacturer's tool. Time constants for timing (reset delays, debounce) have the same problem, plus X7R's ±15 % over temperature.

Common mistakes

• Forgetting the source. An RC fed from a 10 kΩ potentiometer wiper or a high-impedance divider has R equal to whatever that is plus your resistor, and the corner is not where the schematic says.
• Putting a 100 kΩ RC in front of an ADC. The multiplexed input charges C_hold from your capacitor, then your capacitor recharges through 100 kΩ. If the channel is scanned faster than that recovers, the reading is low and depends on the previous channel.
• Assuming an RC on a logic line "just slows it down". 2.2 τ against a 2 ns edge with 100 Ω and 100 pF is 22 ns; the receiver sees a slow ramp through its threshold and, without hysteresis, can double-clock. Series R alone, or a Schmitt input, for that job.
• Stacking two RCs and expecting the second-order roll-off. See above; the unbuffered pair is −9.5 dB at the corner you designed for and has no sharp knee.
• Rating C at nominal on a biased node. The 100 nF that filters a 12 V sense line through a 0402 16 V X5R might be 40 nF.

Further reading

• Würth ANP062, LC Filter Design With MLCCs: Why the Applied Voltage Matters — DC-bias curves by package and rating; the reason your 100 nF is not 100 nF.
• TI SBAA113, PCB Layout for Low-Distortion High-Speed ADC Drivers — the RC in front of an ADC as charge reservoir, and how to pick it.
• TI SCBA007, The Bypass Capacitor in High-Speed Environments — ESL, ESR and self-resonance, i.e. why the roll-off flattens out at high frequency.
• ADI MT-101, Decoupling Techniques — capacitor parasitics and the impedance-versus-frequency view that makes the single-pole model's limits obvious.