Microstrip and stripline impedance

What it computes

The characteristic impedance of a trace from its geometry, using the closed-form equations in IPC-2141A (Design Guide for High-Speed Controlled Impedance Circuit Boards, Section 4). These are curve fits to field-solver output from the 1990s, good to a few percent inside their fitted range and increasingly wrong outside it.

Surface microstrip — a trace on an outer layer over one reference plane:

Z0     = 87 / √(εr + 1.41) · ln( 5.98·H / (0.8·W + T) )
εr_eff = 0.475 · εr + 0.67
t_pd   = 85 · √εr_eff                      ps per inch
Zdiff  = 2 · Z0 · (1 − 0.48 · e^(−0.96·S/H))     edge-coupled pair

W trace width, H dielectric height to the plane, T copper thickness, S edge gap

Symmetric stripline — a trace centred between two planes:

Z0    = 60 / √εr · ln( 4·H / (0.67·π · (0.8·W + T)) )
Zdiff = 2 · Z0 · (1 − 0.374 · e^(−2.9·S/H))
t_pd  = 85 · √εr

H here is plane-to-plane spacing, not trace-to-plane

Stripline has no air above it, so the effective dielectric constant is just εr and the line is slower than a microstrip on the same laminate. The differential correction factor decays faster (2.9 vs 0.96) because the planes on both sides screen the coupling.

Solve for width inverts the single-ended equation. Both forms are Z0 = K · ln(N / (0.8W + T)), so

0.8·W + T = N / e^(Z0/K)
W = (N / e^(Z0/K) − T) / 0.8       N = 5.98H (microstrip) or 4H/(0.67π) (stripline)

The differential result is then reported at the width found and the spacing you entered; it does not iterate on the spacing.

Worked example

Microstrip: 10 mil trace, 6 mil FR-4 prepreg (εr = 4.3), 1 oz copper (1.378 mil), 8 mil gap for the pair.

0.8·W + T   = 8 + 1.378 = 9.378
5.98·H      = 35.88
ratio       = 35.88 / 9.378 = 3.826
ln(3.826)   = 1.342
√(εr+1.41)  = √5.71 = 2.390
87 / 2.390  = 36.41
Z0          = 36.41 · 1.342 = 48.9 Ω

εr_eff      = 0.475 · 4.3 + 0.67 = 2.713
t_pd        = 85 · √2.713 = 85 · 1.647 = 140 ps/in

S/H         = 8 / 6 = 1.333
e^(−0.96 · 1.333) = e^(−1.28) = 0.278
1 − 0.48 · 0.278  = 0.867
Zdiff       = 2 · 48.9 · 0.867 = 84.7 Ω

W/H = 1.67, inside the fit. To hit 50 Ω exactly on this stack the solver goes the other way:

Z0 / K      = 50 / 36.41 = 1.373
e^1.373     = 3.948
35.88 / 3.948 = 9.087
W           = (9.087 − 1.378) / 0.8 = 9.64 mil

Stripline on the same board: 5 mil trace centred between planes 20 mil apart, εr = 4.2, 1 oz copper, 8 mil gap.

0.8·W + T      = 4 + 1.378 = 5.378
0.67·π · 5.378 = 11.32
4·H / 11.32    = 80 / 11.32 = 7.067
ln(7.067)      = 1.955
60 / √4.2      = 60 / 2.049 = 29.28
Z0             = 29.28 · 1.955 = 57.2 Ω

S/H            = 8 / 20 = 0.4
e^(−2.9 · 0.4) = e^(−1.16) = 0.313
1 − 0.374 · 0.313 = 0.883
Zdiff          = 2 · 57.2 · 0.883 = 101 Ω

W/H = 0.25, inside the stripline fit's W/H < 0.35 limit. At 8 mil gap the pair is weakly coupled and Zdiff is close to 2·Z0; tighten to a 5 mil gap and it drops to 94 Ω.

Where it stops being valid

• Microstrip: 0.1 < W/H < 2.0 and 1 < εr < 15. The tool flags anything outside that. Below W/H = 0.1 the fit undershoots; above 2 it overshoots, and the logarithm goes negative once 0.8W + T exceeds 5.98H — a 40 mil trace over 4 mil prepreg returns a negative impedance, which the tool refuses to present as a number.
• Thin dielectrics. Under about 4 mil the copper thickness term (0.8W + T) starts dominating and the equation loses several ohms against a field solver. Modern 4-layer stackups with 3–4 mil prepreg under the outer layers sit right at this edge; expect the IPC form to read 2–4 Ω high for a 50 Ω line.
• Stripline: W/H < 0.35 and T/H < 0.25. Wide traces between closely spaced planes are outside the fit. Asymmetric stripline (trace nearer one plane, the usual case in a 6-layer board) needs the separate IPC-2141 asymmetric equation or a solver; the symmetric form is optimistic there.
• The εr_eff line is a linear fit. 0.475·εr + 0.67 ignores W/H entirely. Hammerstad–Jensen gives the geometry-dependent value; the difference is a few percent in delay, which matters for length matching at DDR speeds, not for whether the line is 50 Ω.
• Solder mask, weave and frequency. Mask over a microstrip drops Z0 by 1–3 Ω. FR-4's εr is 4.5 at 1 MHz and closer to 4.0 at 5 GHz and varies with glass style and resin content; your fab's stackup sheet gives the number they actually measured. Coated microstrip has its own IPC-2141 correction the tool does not apply.
• Use a solver when the number has to be right. The free ones are good: the KiCad PCB Calculator (transmission-line tab, from the Transcalc code), Saturn PCB Toolkit, and every serious fab's online stackup tool. The fab's tool is the one to trust, because they will adjust the trace width at CAM to hit your impedance anyway; what you need from this page is a width within 10–20 % of the answer so the layout does not have to be redone.

Common mistakes

• Stripline H. The equation wants plane-to-plane spacing. Entering the trace-to-nearest-plane distance halves H and reports an impedance 20 Ω low.
• Using nominal copper thickness for outer layers. Outer copper is plated up; a "1 oz" outer layer is often 1.7–2 mil finished. Inner layers are the foil weight as stated. A mil of extra T moves a 50 Ω microstrip by about 1.5 Ω.
• Reference plane that isn't one. The formula assumes a solid plane directly under the trace. Routing over a split, a slot, or a power plane with cutouts changes Z0 and, worse, the return path. Check the layer below before trusting the number.
• Differential impedance without thinking about coupling. A 100 Ω pair at S/H = 2 is two 50 Ω lines that barely notice each other, which is fine for USB and poor for anything where common-mode rejection matters. Tightly coupled (S ≈ W) needs narrower traces to hold 100 Ω; the tool does not re-solve W for a target Zdiff.
• Chasing the third digit. Etch tolerance is ±0.5–1 mil, prepreg thickness ±10 %, εr ±0.2. A controlled-impedance spec of ±10 % is normal; ±5 % costs extra and needs coupon testing. Pick a width, round it to something the fab likes, and write the impedance on the drawing.
• Mixing mils and mm. The equations are ratios so any consistent unit works, but 1.378 mil of copper next to a 0.15 mm height is a common way to get a nonsense answer.

Further reading

• IPC-2141A— the source of all four equations plus the embedded, coated and asymmetric-stripline variants.
• TI SPRAAR7, High-Speed Interface Layout Guidelines— stackups, impedance targets, spacing and length matching for DDR, USB, PCIe and the like.
• KiCad PCB Calculator, transmission lines— free, includes stripline, coplanar and coupled lines with a more accurate (Hammerstad/Kirschning) microstrip model.
• Saturn PCB Design Toolkit— free Windows tool with impedance, differential, crosstalk and via calculators; cites its sources per calculator.