Crystal load capacitance
A crystal is trimmed to run on-frequency into one specific load. The two capacitors on the MCU pins have to present that load, after the stray capacitance of the pins and traces is counted. Get it wrong and the oscillator still starts — just off frequency, and your RTC drifts.
The load the crystal was trimmed against, from its datasheet — 8, 12.5 or 20 pF are the usual ones. Load it with anything else and it runs off frequency, which is what this calculator is for.
Everything on one leg that is not the load capacitor: the pin capacitance of the oscillator (typically 3–5 pF) plus the PCB trace. Keep the traces short and this stays small and predictable.
Nominal frequency, used for drive level and for the gain margin check. It does not affect the load capacitor arithmetic.
Shunt (static) capacitance across the crystal package, typically 1–7 pF. Needed for the pullability and negative-resistance figures.
Motional capacitance, in femtofarads — a few fF, four to five orders below C0. It sets how far the crystal can be pulled by the load.
Maximum equivalent series resistance from the datasheet. The oscillator must present at least about five times this as negative resistance for a reliable start.
Transconductance of the oscillator inverter, from the MCU datasheet. Compare it against the critical gm this reports; five times is the usual margin.
Measured swing across the crystal, taken with a low-capacitance active probe — a 10 pF passive probe loads the node enough to change what you are measuring.
Maximum drive level the crystal can take, usually 100 µW for a small watch or MHz part. Overdriving ages it and can fracture the blank; add a series resistor if you exceed it.
- C1 = C2, exact
- 22.0 pF
- Nearest E12 value
- 22 pF
- Load seen with 22 pF
- 12.50 pF (-0.00 pF)
What it computes
A crystal is trimmed at the factory to sit on its nominal frequency when it sees one specific capacitance across its terminals: the rated load CL, printed on the datasheet as 8, 9, 12.5, 18 or 20 pF. In a Pierce oscillator the crystal sees the two pin capacitors in series, and on each side the pin, pad and trace stray capacitance sits in parallel with the capacitor you fitted. So the load the crystal actually gets is
C_L = (C1 + C_s) · (C2 + C_s) / (C1 + C2 + 2·C_s)
with C1 = C2 = C: C_L = (C + C_s) / 2
solve for C: C = 2·C_L − C_sCs is the stray per side. The MCU datasheet gives the pin capacitance (2 to 4 pF is normal); a short trace and its pad add another 1 to 2 pF. This is the form inST AN2867, Oscillator design guide for STM8 and STM32, section 3.4, and in TI SWRA372 section 4. The tool rounds C to the nearest E12 value and then reports the load you actually get with that part.
Two more checks from AN2867 decide whether the oscillator starts at all, and the tool runs both when you supply ESR, C0 and the MCU's transconductance.
Gain margin (AN2867 §3.3):
gm_crit = 4 · ESR · (2π·f)² · (C0 + C_L)²
margin = gm / gm_crit needs > 5
Drive level (AN2867 §3.5):
C_tot = C0 + C_L
I_pk = π · f · C_tot · V_pp current through the crystal
DL = ESR · I_pk² / 2 = ESR · I_rms²
compare against the crystal's rated DL (100 µW MHz, 0.5–1 µW tuning fork)Frequency pulling is the last output. With Cm and C0from the crystal datasheet, the slope of frequency against load at the rated CL is
df/dC_L = −f · C_m / (2 · (C0 + C_L)²) Hz per farad; the tool shows Hz/pFWorked example
8 MHz crystal, CL = 10 pF, ESR 80 Ω, C0 = 5 pF, Cm = 20 fF. Stray per side estimated at 3 pF. MCU HSE transconductance 25 mA/V.
C = 2 × 10 − 3 = 17 pF nearest E12: 18 pF (15 is further)
Load with 18 pF:
C_L' = (18 + 3) / 2 = 10.5 pF error +0.5 pF
Pulling slope:
df/dC = 8e6 × 20e-15 / (2 × (5e-12 + 10e-12)²)
= 1.6e-7 / (2 × 2.25e-22)
= 3.56e14 Hz/F = 356 Hz/pF
Δf = 356 × 0.5 = 178 Hz → 178 / 8e6 = 22 ppm
Gain margin:
(2π × 8e6)² = 2.527e15
(C0 + C_L)² = (15e-12)² = 2.25e-22
gm_crit = 4 × 80 × 2.527e15 × 2.25e-22 = 1.82e-4 A/V = 0.182 mA/V
margin = 25 / 0.182 = 137 (> 5, starts with room to spare)
Drive level, 1.0 V pk-pk measured at the crystal:
I_pk = π × 8e6 × 15e-12 × 1.0 = 377 µA
DL = 80 × (377e-6)² / 2 = 5.7 µW (rated 100 µW, fine)The calculator reports 17.0 pF exact, 18 pF E12, 10.50 pF seen, +0.50 pF error, 356 Hz/pF and 22.2 ppm. The extra half picofarad of load pulls the crystal 22 ppm below nominal, which is already the whole tolerance budget on many parts. 15 pF would land at 9.0 pF and −1.0 pF the other way; fitting one 15 and one 18 gets within 0.25 pF, and that is the one case where an asymmetric pair earns its keep.
Where it stops being valid
32.768 kHz is a different animal. The formulas are the same; the numbers are not. A tuning-fork crystal has an ESR of 35 to 90 kΩ, a C0 around 1.3 pF and a drive rating of 0.5 to 1 µW. Run the gain-margin check on a 70 kΩ, 12.5 pF part and gmcrit comes out around 2.3 µA/V. A low-power LSE driver offers only a few µA/V, so the same MCU that has a margin of 137 on its HSE can be at 2 on its LSE and fail to start cold. Drop to a 6 or 7 pF crystal, or turn the driver strength up one step and accept the extra hundred nanoamps. Conversely a driver set too strong overdrives the fork and ages it; the frequency walks.
Why RTC crystals drift anyway. A tuning fork's temperature curve is a parabola centred at 25 °C, about −0.035 ppm/°C². At 0 °C it is 22 ppm low; at −20 °C, 71 ppm, which is six seconds a day. No load capacitor fixes that; you need temperature compensation in firmware or a TCXO. The load error on top of it is what this tool controls, and at 32 kHz the sensitivity is worse because C0 is so small: the same 0.5 pF error is typically 15 to 25 ppm.
The gain-margin formula is conservative. AN2867 derives it for the crystal's own C0 plus CL; a probe on the pin adds its own capacitance to both the load and the drive calculation, so measure Vpp with a sub-1 pF active probe or accept that the measurement itself moves the number. Margins between 3 and 5 often start fine on the bench and fail at −40 °C or on a part from a different lot. Any series Rext on the driver output adds to ESR.
Measuring the stray instead of guessing. Fit the calculated capacitors, run the oscillator, and read the frequency on a counter through a buffered output (MCO pin, not a probe on the crystal). Convert the error back to capacitance with the pulling slope. In the example, 356 Hz/pF is 44 ppm/pF, so a measured −20 ppm means the crystal sees 0.45 pF more load than assumed, which is 0.9 pF more stray per side since CL = (C + Cs)/2. Rerun the tool with Cs = 3.9 pF and pick again. One iteration is enough.
Common mistakes
- Fitting C1 = C2 = CL. Two 12.5 pF caps in series are 6.25 pF, plus stray gives about 9 pF, and the crystal runs 100 ppm or more high. The external value is roughly twice CL, less stray.
- Copying the reference-design values onto a different layout. Those 20 pF parts were chosen for that board's stray and that crystal's CL. Change either and the number changes.
- Using X7R or X5R. Their capacitance moves 15 % over temperature and more with voltage. Load capacitors are C0G/NP0 only, ±5 % or better.
- Ignoring drive level on a tuning fork. 1 µW is very little; an HSE-class driver, or a strong LSE setting, blows straight past it and the crystal ages several ppm a year. Check it, and add Rext if needed.
- Long traces or a via to the crystal, or a ground pour under it with no guard. The stray is no longer 3 pF and it is not the same on both sides. Keep the crystal within a few millimetres of the pins; AVR186 has the layout rules.
Further reading
- ST AN2867, Oscillator design guide for STM8 and STM32 — load, gain margin, drive level and Rext, with a full 32 kHz worked example.
- TI SWRA372, AN100 Crystal Selection Guide — the same load formula, plus ESR and drive-level limits table by frequency.
- TI SNAA065, AN-1939 Crystal Based Oscillator Design — Pierce theory and negative resistance, the basis of the gain-margin test.
- Microchip AVR186, PCB layout of oscillators — guard ring, ground fill and trace length rules that keep the stray predictable.