I²C pull-up

What it computes

An I²C line is open-drain. Nothing drives it high; the pull-up does, through whatever capacitance hangs on the line. That gives the resistor a floor and a ceiling, and the tool reports both.

The floor comes from the low level. When a device pulls the line down it has to sink the pull-up current and still hold the line at or below V_OL. NXP UM10204 section 6.1 (Table 9) rates the driver at 3 mA for Standard- and Fast-mode, 20 mA for Fast-mode Plus, with V_OL = 0.4 V. Go below R_min and the low level creeps up towards the input threshold.

The ceiling comes from the rise time. UM10204 Table 10 limits t_r to 1000 ns, 300 ns and 120 ns for the three modes, and defines it between 30 % and 70 % of V_DD, not 10 % to 90 %. For an RC edge, the time between those two points is ln(0.7/0.3) = 0.8473 time constants. That constant is the whole difference between this calculator and one that multiplies by 2.2.

R_min = (V_DD − V_OL) / I_OL             I_OL = 3 mA (SM, FM), 20 mA (FM+)
R_max = t_r(max) / (0.8473 · C_b)        t_r(max) = 1000 / 300 / 120 ns
t_r   = 0.8473 · R_p · C_b               rise time with the resistor you chose
I_low = (V_DD − V_OL) / R_p              current per line while it is held low
P     = V_DD · I_low                     per line; SDA and SCL both need one

Bus capacitance C_b is the total on one line: every device pin, the MCU pin, the pads and the copper. UM10204 caps it at 400 pF (550 pF for FM+). If you have not measured it, budget 10 pF per device pin (the specification's own allowance, section 6.1) plus roughly 1 pF per centimetre of trace over a ground plane. The tool builds C_b from those two terms so the estimate is at least visible.

The same formulas, with the same constants, appear inTI SLVA689, I²C Bus Pullup Resistor Calculation, section 2 and 3. The source isNXP UM10204, I²C-bus specification and user manual, section 7.1.

Worked example

Fast-mode at 400 kHz, 3.3 V rail. Six devices on the bus (the MCU plus five peripherals), 30 cm of total SDA copper across a small backplane.

C_b   = 6 × 10 pF + 30 cm × 1 pF/cm = 60 + 30 = 90 pF

R_min = (3.3 − 0.4) / 3 mA
      = 2.9 / 0.003
      = 967 Ω

R_max = 300 ns / (0.8473 × 90 pF)
      = 300e-9 / 76.26e-12
      = 3.93 kΩ

Geometric middle = √(967 × 3934) = 1950 Ω  →  nearest E24: 2.0 kΩ

Fit a 2.2 kΩ (what was in the reel) and check it:

t_r   = 0.8473 × 2200 × 90e-12 = 168 ns          (limit 300 ns, fine)
I_low = 2.9 / 2200              = 1.32 mA         (limit 3 mA, fine)
P     = 3.3 × 1.32 mA           = 4.35 mW per line
Both lines held low             = 8.70 mW

The calculator gives R_min 967 Ω, R_max 3.93 kΩ, suggested 2.0 kΩ, and 168 ns / 1.32 mA / 4.35 mW for the 2.2 kΩ choice. The 8.7 mW is the worst case, both lines low; average power on an idle bus is close to zero since both lines sit high.

Where it stops being valid

The model is a single RC. It is right as long as the line is electrically short, which at I²C speeds is always true on a PCB, and it is right as long as the only thing pulling up is the resistor. Three things break it:

• Internal pull-ups. Many peripherals and every MCU port have optional weak pull-ups, 20 kΩ to 100 kΩ. In parallel with your 2.2 kΩ they move the number a little; left on by accident with no external resistor at all, the bus has a 50 kΩ pull-up and a rise time in the microseconds. Standard-mode may still work. Fast-mode will not.
• Level shifting. A mixed 3.3 V / 5 V bus with a MOSFET shifter (NXP AN10441, or a PCA9306) is two buses. Each side gets its own pull-up to its own rail, sized for its own capacitance. The FET adds a few picofarads and a body-diode path; it does not merge the two RC problems into one. A 5 V-tolerant device on a 3.3 V bus is not a level-shifting problem at all: it is simply on the 3.3 V bus and uses 3.3 V in the formula.
• Cables and long buses. Once the run goes off-board, 1 pF/cm turns into 50 to 100 pF per metre of cable and C_b blows past 400 pF fast. When R_max drops below R_min the tool says so: no resistor works. The fixes are a buffer (PCA9515 / P82B715), Standard-mode instead of Fast-mode, or a different bus.

This is why the 4.7 kΩ everyone has in the drawer fails at 400 kHz. It was a fine Standard-mode value on a short 5 V bus. On the 90 pF bus above it gives 0.8473 × 4700 × 90 pF = 358 ns, already over the 300 ns limit; at 200 pF it is 796 ns and the edges are visibly rounded on a scope. At 400 pF it is 1.59 µs, which fails even Standard-mode. Fast-mode with any real bus wants something between 1 kΩ and 2.2 kΩ.

Common mistakes

• Sizing for the pins and forgetting the copper. A 10 cm trace is 10 pF, about one extra device. A ribbon cable to a sensor board can be the whole budget.
• Using 10–90 % rise time. That is 2.2 τ, not 0.85 τ, and the ceiling comes out 2.6 times too low. Scope cursors need to be set to 30 % and 70 % of V_DD to compare against the specification.
• One pull-up shared by two boards. Each board's designer added their own, the parallel combination lands under R_min, and the weakest driver on the bus can no longer reach 0.4 V. Decide who owns the pull-up.
• Pulling up to the wrong rail. The resistor goes to the rail of the lowest V_DD device on that segment, unless every part is documented tolerant of the higher rail.
• Picking the top of the window to save power. The sink current only flows while a line is held low; on a bus that is mostly idle the saving is tiny and the marginal edge is permanent. Sit near the geometric middle.

Further reading

• NXP UM10204, I²C-bus specification and user manual — the source; sections 6 and 7 have the electrical limits and the pull-up derivation.
• TI SLVA689, I²C Bus Pullup Resistor Calculation — the same formulas worked with numbers and a plot of the valid window.
• AN10441, Level shifting techniques in I²C-bus design — the single-FET bidirectional shifter and why each side needs its own pull-up.