Why 100 nF, and the frequency where it stops being a capacitor

Open any schematic and count the 100 nF capacitors. One per supply pin, sometimes two, placed without discussion. It is the most-placed component in electronics and almost nobody can say why that number and not another.

The honest answer is that the value is inherited. It was a sensible choice for TTL on a two-layer board and it propagated, through reference designs and habit, into work where the original reasoning no longer holds. That does not make it wrong — 100 nF is still a reasonable default — but it does mean the number is the least interesting thing about the part.

A capacitor is a series RLC

The component on the board is not the component in the schematic. A real ceramic capacitor is a capacitance in series with a resistance and an inductance:

|Z| = sqrt( ESR² + (2πfL − 1/(2πfC))² )

The capacitive term falls with frequency and the inductive term rises. They cancel at the self-resonant frequency:

f_srf = 1 / (2π · sqrt(L · C))

Below resonance the part behaves like the capacitor you ordered. Above it, the impedance rises at exactly the rate an inductor’s does, and the capacitance value stops appearing in the answer at all. Past resonance the only thing that matters is L.

Put numbers on it. A 100 nF part in an 0402 package, with about 0.4 nH of body inductance and another 0.6 nH from its pads and vias, has roughly 1 nH of total loop inductance:

f_srf = 1 / (2π · sqrt(1 nH · 100 nF)) ≈ 15.9 MHz

Sixteen megahertz. On a board with a 100 MHz clock and 2 ns edges, the capacitor spends most of the spectrum that matters behaving as an inductor. At 500 MHz that 1 nH presents

|Z| ≈ 2πfL = 2π · 500 MHz · 1 nH ≈ 3.1 Ω

Three ohms, from a part chosen to be a short circuit. The decoupling calculator plots this curve for whatever part and mounting you actually have.

Inductance is the design variable

If the useful quantity above resonance is inductance, then the interesting question is what sets it. Kyocera AVX measured this directly for a range of packages (Parasitic Inductance of Multilayer Ceramic Capacitors):

Package	Measured ESL
0603	870 pH
0805	1050 pH
1206	1250 pH
1210	980 pH
0612	610 pH
0508	600 pH

Two things in that table are worth sitting with.

1210 is lower than 1206. They are the same footprint area. The 1210 is wider, so the current spreads through a shorter, fatter loop. Inductance tracks the length-to-width ratio of the current path, not the size of the part.

0612 is half of 1206. A 0612 is a 1206, terminated on its long edges instead of its short ones. Same ceramic, same capacitance, same volume — rotate which edges are the terminals and the inductance drops from 1250 pH to 610 pH. Nothing about the capacitor changed. Only the shape of the loop did.

That is the whole argument in one row of a table. Decoupling is a loop-geometry problem that happens to have a capacitor in it.

Adding a smaller capacitor usually does not help

The traditional fix for “the 100 nF runs out at 16 MHz” is to park a 1 nF or a 100 pF next to it. The reasoning is that the smaller part resonates higher, so it covers the gap.

It does resonate higher. It also has almost the same inductance, because inductance is set by the package and the mounting, not the capacitance. Two parts of different values in parallel do not give you a smooth impedance curve — they give you a parallel anti-resonance between the capacitive branch of one and the inductive branch of the other, at which the pair’s impedance is higher than either alone.

Würth built exactly this experiment into their layout test board, putting a 100 pF, a 1 nF and a 4.7 nF in parallel and measuring the insertion loss (ANP098). They expected unfavourable resonances from C0G parts, which are very high-Q, and noted that repeating it with X7R gives a less pronounced resonance because the barium titanate dielectric is lossier and damps it.

Which is the useful conclusion: if you do mix values, the lossy dielectric you were told to avoid is the one that saves you. But mostly, do not mix values. More of the same part, mounted well lowers impedance everywhere without inventing a peak, because n identical capacitors in parallel have L/n.

What to do instead

Stop choosing a value and start choosing a target impedance. The rail has to hold its ripple budget against the load step the silicon actually draws:

Z_target = V_dd · ripple / ΔI        f_max ≈ 0.35 / t_rise

A 3.3 V rail allowed 5 % ripple against a 1 A step needs to stay under 165 mΩ, and it needs to stay there up to the frequency the edges reach — for a 2 ns edge, about 175 MHz. Now the question “how many capacitors, in what package, mounted how” has an answer you can check, rather than a convention you inherited.

TI made the same point with a scope rather than a network analyser back in 1996 (SCBA007): an ABT541 with eight outputs switching needs about 400 mA delivered within the roughly 3 ns output rise time, and they measured the resulting rail disturbance with capacitors at 0.3, 1 and 2 inches from the power pin. The capacitor value mattered far less than how far away it was.

Which is the next article’s problem: almost all of the inductance in that 1 nH is not in the capacitor.

Sources

• Kyocera AVX — Parasitic Inductance of Multilayer Ceramic Capacitors — measured ESL by package, and the length-to-width curve fit behind it.
• TI SCBA007 — The Bypass Capacitor in High-Speed Environments — the transient-charge argument and measured rail disturbance versus distance.
• Würth ANP098 — Effect of layout, vias and design on the blocking quality of filter capacitors — insertion-loss measurements, including parallel values of one dielectric class.
• Würth ANP109 — Impedance Spectra of Different Capacitor Technologies — measured impedance curves across capacitor families.
• TI SPRA230 — Guidelines for Using Decoupling Capacitors on DSP Designs — value selection, bulk versus local.